Difference between revisions of "Gemini IVC Problems"

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[[File: IVC1.jpg|thumb|CRTC Pin 21 (CLK)]]
+
[[File:D0-D7.jpg|thumb|Activity of D0 to D7 respectively]]
[[File: IVC2.jpg|thumb|CRTC Pin 24 (R/S)]]
+
 
[[File: IVC3.jpg|thumb|CRTC Pin 22 (R/W)]]
 
[[File: IVC4.jpg|thumb|MUX ICs (10,11,12,15,16,17) Pin 1]]
 
[[File: IVC5.jpg|thumb|Video Ram IC9 Pin 21 (/WE)]]
 
[[File: IVC6.jpg|thumb|Video Ram IC9 Pin 20 (/OE)]]
 
[[File: IVC5.jpg|thumb|Char Gen IC20 Pin 21 (/WE)]]
 
[[File: IVC6.jpg|thumb|Char Gen IC20 Pin 20 (/OE)]]
 
[[File: IVC7.jpg|thumb|CPU RAM IC 13 Pin 18 (/CS)]]
 
[[File: IVC8.jpg|thumb|CPU RAM IC 13 Pin 20 (/OE)]]
 
[[File: IVC9.jpg|thumb|CPU RAM IC 13 Pin 21 (/WE)]]
 
 
[[File: IVC1-7.jpg|thumb]]
 
[[File: IVC1-7.jpg|thumb]]
During the process of restoring a Gemini 80 Bus computer I had an issue with the Gemini IVC video card see [[The Gemini 80-Bus Saga]].
 
  
In order to further test the IVC card, a test ROMS was created designed to replace the IVC MON ROM. The code was designed to test the addressing and whilst the idea came from multiple sources over on https://www.vintage-radio.net, the final code was provided to me by Neal Crook.
+
During my Gemini journey (see [[The Gemini 80-Bus Saga]]), I was originally thwarted by a faulty GM812 IVC video card which failed a couple of weeks after I purchased the machine in May 2019. This tied in nicely with obtaining a working CP/M disk, except it didn't, as the CP/M version required the IVC Doh! Thankfully, as described earlier, CP/M could be patched to use the serial port for TTY by changing a couple of bytes so I was off and running. However, in parallel with using a serial terminal to talk to the Gemini CP/M, I set about fixing the IVC card.
 +
 
 +
I started by testing the CRTC in a BBC Micro, and the Z80 in a BBC Second processor, the CRTC worked fine, however, the Z80 failed miserably. I popped a replacement CPU (remarkably with a date code only 2 weeks from that of the original) into the IVC thinking that I had effected a repair only to discover that all I had were different symptoms i.e. a different kind of flashing on the screen and still no video.
 +
 
 +
After going around the houses and few false starts, I isolated the issue to the strobe that is meant to activate a read or write to the CRTC, the problem was that ther wasn't one. Things were getting technical, but by removing the CRTC and the CPU I had isolated enough connections to be able to manually test IC 31 a D-Type Flip Flop which under control of the clock strobes the CRTC, it wasn't working. As this was a soldered in chip, on went the soldering iron and out came the enamelled wire (see image fo how enamelled wire). If you are not familiar with this method of removing solder from through plated holes, here's how I used it when undertaking an Apple IIe RAM swap [[Apple_IIe_RAM_Swap_the_Easy_Way]]. Naturally a decent socket was fitted with a new SN74S74 D-Type Flip Flop, alas, the card was still not working correctly and I started to think that it had been hit by lightning.
 +
 
 +
In order to further test the IVC card, a test ROM was created designed to replace the IVC MON ROM. The code was designed to test the addressing. The idea came from multiple sources over on https://www.vintage-radio.net, the final code was provided to me by Neal Crook.
 +
 
 +
    0000                    ;; in ROM and executes from reset.
 +
    0000                    ;; assume no stack/working RAM so no subroutines
 +
    0000                    ORG 0
 +
    0000                   
 +
    0000 db 00      loop:  in a, (0)        ; should generate /CS to 6845.
 +
                                            ; Also, use as 'scope trigger
 +
    0002 21 00 20          ld hl, 0x2000    ; video RAM
 +
    0005 7e                ld a, (hl)      ; read then write
 +
    0006 77                ld (hl), a
 +
    0007 21 00 40          ld hl, 0x4000    ; char gen ROM or RAM
 +
    000a 7e                ld a, (hl)      ; read then write
 +
    000b 77                ld (hl), a
 +
    000c 21 00 60          ld hl, 0x6000    ; status read
 +
    000f 7e                ld a, (hl)      ; read
 +
    0010 21 00 80          ld hl, 0x8000    ; keyboard
 +
    0013 7e                ld a, (hl)      ; read
 +
    0014 21 00 a0          ld hl, 0xa000    ; host comms data port
 +
    0017 7e                ld a, (hl)      ; read then write
 +
    0018 77                ld (hl), a
 +
    0019 21 00 c0          ld hl, 0xc000    ; status write
 +
    001c af                xor a
 +
    001d 77                ld (hl), a      ; write 0
 +
    001e 21 00 e0          ld hl, 0xe000    ; workspace RAM
 +
    0021 7e                ld a, (hl)      ; read then write
 +
    0022 77                ld (hl), a
 +
    0023 18 db              jr loop
 +
    0025
 +
 
 +
==Data Bus Activity==
 +
 
 +
Once the ROM was installed and running, the first thing I did was check the data bus activity. The first block of images shows the activity of D0 to D7 respectively.
 +
 
 +
==Address Everything Test==
  
 
The memory map of the IVC system  is as follows;
 
The memory map of the IVC system  is as follows;
Line 22: Line 52:
 
     6000 - 7FFF STATUS (RD)    E000 - FFFF RAM
 
     6000 - 7FFF STATUS (RD)    E000 - FFFF RAM
  
This was the test code provided by Neal to access the various memory mapped components. This was burnt into a 2732a EPROM and was used in place of the standard IVC MON ROM.
 
  
    0000                            ;; in ROM and executes from reset.
+
The second block of images show the results of wandering around the various component with an oscilloscope and taken from left to right, top to bottom, they depict the following;
    0000                            ;; assume no stack/working RAM so no subroutines
 
    0000                            ORG 0
 
    0000                   
 
    0000 db 00              loop:  in a, (0)              ; should generate /CS to 6845.
 
                                                            ; Also, use as 'scope trigger
 
    0002 21 00 20                  ld hl, 0x2000          ; video RAM
 
    0005 7e                        ld a, (hl)              ; read then write
 
    0006 77                        ld (hl), a
 
    0007 21 00 40                  ld hl, 0x4000          ; char gen ROM or RAM
 
    000a 7e                        ld a, (hl)              ; read then write
 
    000b 77                        ld (hl), a
 
    000c 21 00 60                  ld hl, 0x6000          ; status read
 
    000f 7e                        ld a, (hl)              ; read
 
    0010 21 00 80                  ld hl, 0x8000          ; keyboard
 
    0013 7e                        ld a, (hl)              ; read
 
    0014 21 00 a0                  ld hl, 0xa000          ; host comms data port
 
    0017 7e                        ld a, (hl)              ; read then write
 
    0018 77                        ld (hl), a
 
    0019 21 00 c0                  ld hl, 0xc000          ; status write
 
    001c af                        xor a
 
    001d 77                        ld (hl), a              ; write 0
 
    001e 21 00 e0                  ld hl, 0xe000          ; workspace RAM
 
    0021 7e                        ld a, (hl)              ; read then write
 
    0022 77                        ld (hl), a
 
    0023 18 db                      jr loop
 
    0025
 
 
 
The first block of images show the results of wandering around the various component with an oscilloscope and taken from left to right, top to bottom, they depict the following;
 
  
 
* CRTC Pin 24 (R/S)
 
* CRTC Pin 24 (R/S)
Line 65: Line 66:
 
The scope images for Char Gen IC20 Pin 21 (/WE) are identical to Video Ram IC9 Pin 21 (/WE).
 
The scope images for Char Gen IC20 Pin 21 (/WE) are identical to Video Ram IC9 Pin 21 (/WE).
 
The scope images for Char Gen IC20 Pin 20 (/OE) are identical to Video Ram IC9 Pin 20 (/0E).
 
The scope images for Char Gen IC20 Pin 20 (/OE) are identical to Video Ram IC9 Pin 20 (/0E).
 
 
 
 
 
[[File:D0-D7.jpg|thumb]]
 

Revision as of 20:11, 12 July 2019

Activity of D0 to D7 respectively
IVC1-7.jpg

During my Gemini journey (see The Gemini 80-Bus Saga), I was originally thwarted by a faulty GM812 IVC video card which failed a couple of weeks after I purchased the machine in May 2019. This tied in nicely with obtaining a working CP/M disk, except it didn't, as the CP/M version required the IVC Doh! Thankfully, as described earlier, CP/M could be patched to use the serial port for TTY by changing a couple of bytes so I was off and running. However, in parallel with using a serial terminal to talk to the Gemini CP/M, I set about fixing the IVC card.

I started by testing the CRTC in a BBC Micro, and the Z80 in a BBC Second processor, the CRTC worked fine, however, the Z80 failed miserably. I popped a replacement CPU (remarkably with a date code only 2 weeks from that of the original) into the IVC thinking that I had effected a repair only to discover that all I had were different symptoms i.e. a different kind of flashing on the screen and still no video.

After going around the houses and few false starts, I isolated the issue to the strobe that is meant to activate a read or write to the CRTC, the problem was that ther wasn't one. Things were getting technical, but by removing the CRTC and the CPU I had isolated enough connections to be able to manually test IC 31 a D-Type Flip Flop which under control of the clock strobes the CRTC, it wasn't working. As this was a soldered in chip, on went the soldering iron and out came the enamelled wire (see image fo how enamelled wire). If you are not familiar with this method of removing solder from through plated holes, here's how I used it when undertaking an Apple IIe RAM swap Apple_IIe_RAM_Swap_the_Easy_Way. Naturally a decent socket was fitted with a new SN74S74 D-Type Flip Flop, alas, the card was still not working correctly and I started to think that it had been hit by lightning.

In order to further test the IVC card, a test ROM was created designed to replace the IVC MON ROM. The code was designed to test the addressing. The idea came from multiple sources over on https://www.vintage-radio.net, the final code was provided to me by Neal Crook.

   0000                    ;; in ROM and executes from reset. 
   0000                    ;; assume no stack/working RAM so no subroutines 
   0000                    ORG 0 
   0000                     
   0000 db 00      loop:   in a, (0)        ; should generate /CS to 6845. 
                                            ; Also, use as 'scope trigger 
   0002 21 00 20           ld hl, 0x2000    ; video RAM 
   0005 7e                 ld a, (hl)       ; read then write 
   0006 77                 ld (hl), a 
   0007 21 00 40           ld hl, 0x4000    ; char gen ROM or RAM 
   000a 7e                 ld a, (hl)       ; read then write 
   000b 77                 ld (hl), a 
   000c 21 00 60           ld hl, 0x6000    ; status read 
   000f 7e                 ld a, (hl)       ; read 
   0010 21 00 80           ld hl, 0x8000    ; keyboard 
   0013 7e                 ld a, (hl)       ; read 
   0014 21 00 a0           ld hl, 0xa000    ; host comms data port 
   0017 7e                 ld a, (hl)       ; read then write 
   0018 77                 ld (hl), a 
   0019 21 00 c0           ld hl, 0xc000    ; status write 
   001c af                 xor a 
   001d 77                 ld (hl), a       ; write 0 
   001e 21 00 e0           ld hl, 0xe000    ; workspace RAM 
   0021 7e                 ld a, (hl)       ; read then write 
   0022 77                 ld (hl), a 
   0023 18 db              jr loop 
   0025

Data Bus Activity

Once the ROM was installed and running, the first thing I did was check the data bus activity. The first block of images shows the activity of D0 to D7 respectively.

Address Everything Test

The memory map of the IVC system is as follows;

   0000 - 1FFF ROM            8000 - 9FFF KEYBOARD
   2000 - 3FFF VDU RAM        A000 - BFFF DATA PORT
   4000 - 5FFF CHAR GEN       C000 - DFFF STATUS (WR)
   6000 - 7FFF STATUS (RD)    E000 - FFFF RAM


The second block of images show the results of wandering around the various component with an oscilloscope and taken from left to right, top to bottom, they depict the following;

  • CRTC Pin 24 (R/S)
  • CRTC Pin 22 (R/W)
  • MUX ICs (10,11,12,15,16,17) Pin 1
  • Video Ram IC9 Pin 21 (/WE)
  • Video Ram IC9 Pin 20 (/OE)
  • CPU RAM IC 13 Pin 18 (/CS)
  • CPU RAM IC 13 Pin 20 (/OE)
  • CPU RAM IC 13 Pin 21 (/WE)

The scope images for Char Gen IC20 Pin 21 (/WE) are identical to Video Ram IC9 Pin 21 (/WE). The scope images for Char Gen IC20 Pin 20 (/OE) are identical to Video Ram IC9 Pin 20 (/0E).